CHES 2011:
Tsuyoshi Takagi and Bart Preneel (Eds.):
Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop - CHES 2011,
Nara,
Japan, September 28 -
October 1, 2011
Proceedings.
CHES 2011
Japan, September 28 -
October 1, 2011
Organizational Committee
Program Chairs : | Tsuyoshi Takagi and Bart Preneel | |
General Chair : | Akashi Satoh |
Program Committee
Toru Akishita |
Paulo S. L. M. Barreto |
Lejla Batina |
Daniel J. Bernstein |
Guido Bertoni |
Swarup Bhunia |
Chen-Mou Cheng |
Jean-Sébastien Coron |
Emmanuelle Dottax |
Hermann Drexler |
Martin Feldhofer |
Pierre-Alain Fouque |
Kris Gaj |
Benedikt Gierlichs |
Louis Goubin |
Jorge Guajardo |
Dong-Guk Han |
Helena Handschuh |
M. Anwar Hasan |
Naofumi Homma |
Marc Joye |
Pascal Junod |
Shin-ichi Kawamura |
Paris Kitsos |
Markus G. Kuhn |
Kerstin Lemke-Rust |
Stefan Mangard |
Mitsuru Matsui |
David Naccache |
William D. Neumann |
Elisabeth Oswald |
Christof Paar |
Matthew J. B. Robshaw |
Pankaj Rohatgi |
Ahmad-Reza Sadeghi |
Kazuo Sakiyama |
Erkay Savas |
Patrick Schaumont |
Nigel P. Smart |
Masahiko Takenaka |
Colin D. Walter |
External Referees
-
FPGA Implementation
-
An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
, 1-16,
Johann Großschädl
,
Stefan Tillich
,
Dan Page
,
Philipp Grabher
,
Kimmo Järvinen
,
Simon Hoerder
,
Marcin Wójcik
bib info -
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
, 17-32,
Srinivas Devadas
,
Mehrdad Majzoobi
,
Farinaz Koushanfar
bib info -
Generic Side-Channel Countermeasures for Reconfigurable Devices
, 33-48,
Amir Moradi
,
Tim Güneysu
bib info
-
An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
, 1-16,
Johann Großschädl
,
Stefan Tillich
,
Dan Page
,
Philipp Grabher
,
Kimmo Järvinen
,
Simon Hoerder
,
Marcin Wójcik
-
AES
-
Improved Collision-Correlation Power Analysis on First Order Protected AES
, 49-62,
Christophe Clavier
,
Benoit Feix
,
Georges Gagnerot
,
Vincent Verneuil
,
Mylène Roussellet
bib info -
Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols
, 63-78,
Emmanuel Prouff
,
Thomas Roche
bib info -
Protecting AES with Shamir's Secret Sharing Scheme
, 79-94,
Louis Goubin
,
Ange Martinelli
bib info -
A Fast and Provably Secure Higher-Order Masking of AES S-Box
, 95-107,
Seokhie Hong
,
Jongin Lim
,
HeeSeok Kim
bib info
-
Improved Collision-Correlation Power Analysis on First Order Protected AES
, 49-62,
Christophe Clavier
,
Benoit Feix
,
Georges Gagnerot
,
Vincent Verneuil
,
Mylène Roussellet
-
Elliptic Curve Cryptosystems
-
Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication
, 108-123,
Darrel Hankerson
,
Francisco Rodríguez-Henríquez
,
Julio López
,
Diego F. Aranha
,
Jonathan Taverne
,
Armando Faz-Hernández
bib info -
High-Speed High-Security Signatures
, 124-142,
Daniel J. Bernstein
,
Tanja Lange
,
Bo-Yin Yang
,
Peter Schwabe
,
Niels Duif
bib info -
To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order
, 143-159,
Benedikt Gierlichs
,
Frederik Vercauteren
,
Junfeng Fan
bib info
-
Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication
, 108-123,
Darrel Hankerson
,
Francisco Rodríguez-Henríquez
,
Julio López
,
Diego F. Aranha
,
Jonathan Taverne
,
Armando Faz-Hernández
-
Lattices
-
Random Sampling for Short Lattice Vectors on Graphics Cards
, 160-175,
Michael Schneider
,
Norman Göttert
bib info -
Extreme Enumeration on GPU and in Clouds - - How Many Dollars You Need to Break SVP Challenges -
, 176-191,
Bo-Yin Yang
,
Johannes Buchmann
,
Chen-Mou Cheng
,
Michael Schneider
,
Özgür Dagdelen
,
Po-Chun Kuo
,
Jan Reichelt
bib info -
Modulus Fault Attacks against RSA-CRT Signatures
, 192-206,
David Naccache
,
Phong Q. Nguyen
,
Éric Brier
,
Mehdi Tibouchi
bib info
-
Random Sampling for Short Lattice Vectors on Graphics Cards
, 160-175,
Michael Schneider
,
Norman Göttert
-
Side Channel Attacks
-
Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World
, 207-222,
Christof Paar
,
David Oswald
bib info -
Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box
, 223-239,
François-Xavier Standaert
,
Mathieu Renauld
,
Dina Kamel
,
Denis Flandre
bib info -
Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings
, 240-255,
Emmanuel Prouff
,
Michaël Quisquater
,
Laurie Genelle
bib info -
Extractors against Side-Channel Attacks: Weak or Strong?
, 256-272,
François-Xavier Standaert
,
Marcel Medwed
bib info
-
Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World
, 207-222,
Christof Paar
,
David Oswald
- Invited Talk
-
Fault Attacks
-
Meet-in-the-Middle and Impossible Differential Fault Analysis on AES
, 274-291,
Pierre-Alain Fouque
,
Patrick Derbez
,
Delphine Leresteux
bib info -
On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting
, 292-311,
Kazuo Ohta
,
Christof Paar
,
Amir Moradi
,
Kazuo Sakiyama
,
Oliver Mischke
,
Yang Li
bib info
-
Meet-in-the-Middle and Impossible Differential Fault Analysis on AES
, 274-291,
Pierre-Alain Fouque
,
Patrick Derbez
,
Delphine Leresteux
-
Lightweight Symmetric Algorithms
-
spongent: A Lightweight Hash Function
, 312-325,
Gregor Leander
,
Ingrid Verbauwhede
,
Andrey Bogdanov
,
Kerem Varici
,
Miroslav Knezevic
,
Deniz Toz
bib info -
The LED Block Cipher
, 326-341,
Thomas Peyrin
,
Matthew J. B. Robshaw
,
Axel Poschmann
,
Jian Guo
bib info -
Piccolo: An Ultra-Lightweight Blockcipher
, 342-357,
Taizo Shirai
,
Toru Akishita
,
Kyoji Shibutani
,
Takanori Isobe
,
Harunaga Hiwatari
,
Atsushi Mitsuda
bib info
-
spongent: A Lightweight Hash Function
, 312-325,
Gregor Leander
,
Ingrid Verbauwhede
,
Andrey Bogdanov
,
Kerem Varici
,
Miroslav Knezevic
,
Deniz Toz
-
PUFs
-
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
, 358-373,
Srinivas Devadas
,
David M'Raïhi
,
Meng-Day (Mandel) Yu
,
Richard Sowell
bib info -
Recyclable PUFs: Logically Reconfigurable PUFs
, 374-389,
Ahmad-Reza Sadeghi
,
Geert Jan Schrijen
,
Stefan Katzenbeisser
,
Heike Schröder
,
Ünal Koçabas
,
Vincent van der Leest
,
Christian Wachsmann
bib info -
Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
, 390-406,
Kazuo Ohta
,
Kouichi Itoh
,
Masahiko Takenaka
,
Kazuo Sakiyama
,
Dai Yamamoto
,
Mitsugu Iwamoto
,
Takao Ochiai
bib info -
MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array
, 407-420,
Swarup Bhunia
,
Seetharam Narasimhan
,
Aswin Raghav Krishna
,
Xinmu Wang
bib info
-
Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
, 358-373,
Srinivas Devadas
,
David M'Raïhi
,
Meng-Day (Mandel) Yu
,
Richard Sowell
-
Public-Key Cryptosystems
-
FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction
, 421-441,
Ingrid Verbauwhede
,
Sylvain Duquesne
,
Junfeng Fan
,
Nicolas Guillermin
,
Ray C. C. Cheung
,
Gavin Xiaoxu Yao
bib info -
High Speed Cryptoprocessor for η
T
Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields
, 442-458,
Santosh Ghosh
,
Dipanwita Roy Chowdhury
,
Abhijit Das
bib info -
Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
, 459-474,
Michael Hutter
,
Erich Wenger
bib info -
Small Public Keys and Fast Verification for Multivariate Quadratic Public Key Systems
, 475-490,
Christopher Wolf
,
Stanislav Bulygin
,
Albrecht Petzoldt
,
Enrico Thomae
bib info
-
FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction
, 421-441,
Ingrid Verbauwhede
,
Sylvain Duquesne
,
Junfeng Fan
,
Nicolas Guillermin
,
Ray C. C. Cheung
,
Gavin Xiaoxu Yao
-
Hash Functions
-
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs
, 491-506,
Kris Gaj
,
Marcin Rogawski
,
Ekawat Homsirikamol
bib info -
Efficient Hashing Using the AES Instruction Set
, 507-522,
Martijn Stam
,
Onur Özen
,
Joppe W. Bos
bib info
Author Index -
Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs
, 491-506,
Kris Gaj
,
Marcin Rogawski
,
Ekawat Homsirikamol