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Paper: A High Speed Architecture for Galois/Counter Mode of Operation (GCM)

Authors:
Bo Yang
Sambit Mishra
Ramesh Karri
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URL: http://eprint.iacr.org/2005/146
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Abstract: In this paper we present a fully pipelined high speed hardware architecture for Galois/Counter Mode of Operation (GCM) by analyzing the data dependencies in the GCM algorithm at the architecture level. We show that GCM encryption circuit and GCM authentication circuit have similar critical path delays resulting in an efficient pipeline structure. The proposed GCM architecture yields a throughput of 34 Gbps running at 271 MHz using a 0.18 um CMOS standard cell library.
BibTeX
@misc{eprint-2005-12482,
  title={A High Speed Architecture for Galois/Counter Mode of Operation (GCM)},
  booktitle={IACR Eprint archive},
  keywords={Authenticated Encryption Mode, GCM},
  url={http://eprint.iacr.org/2005/146},
  note={ smishr01@utopia.poly.edu 12937 received 17 May 2005, last revised 3 Jun 2005},
  author={Bo Yang and Sambit Mishra and Ramesh Karri},
  year=2005
}