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FPGA Accelerated Tate Pairing Based Cryptosystems over Binary Fields
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| Abstract: | Though the implementation of the Tate pairing is commonly believed to be computationally more intensive than other cryptographic operations, such as ECC point multiplication, there has been a substantial progress in speeding up the Tate pairing computations. Because of their inherent parallelism, the existing Tate pairing algorithms are very suitable for hardware implementation aimed at achieving a high operation speed. Supersingular elliptic curves over binary fields are good candidates for hardware implementation due to their simple underlying algorithms and binary arithmetic. In this paper we propose efficient Tate pairing implementations over binary fields $\mathbb F_{2^{239}}$ and $\mathbb F_{2^{283}}$ via FPGA. Though our field sizes are larger than those used in earlier architectures with the same security strength based on cubic elliptic curves or binary hyperelliptic curves, fewer multiplications in the underlying field are required, so that the computational latency for one pairing can be reduced. As a result, our pairing accelerators implemented via FPGA can run 15-to-25 times faster than other FPGA realizations at the same level of security strength, and at the same time achieve lower product of latency by area. |
BibTeX
@misc{eprint-2006-21672,
title={FPGA Accelerated Tate Pairing Based Cryptosystems over Binary Fields},
booktitle={IACR Eprint archive},
keywords={implementation / pairing computation, FPGA, binary field},
url={http://eprint.iacr.org/2006/179},
note={ shkwon@skku.edu 13370 received 24 May 2006, last revised 10 Aug 2006},
author={Chang Shu and Soonhak Kwon and Kris Gaj},
year=2006
}