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Paper: Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA

Authors:
Jean-Luc Beuchat
Eiji Okamoto
Teppei Yamazaki
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URL: http://eprint.iacr.org/2010/173
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Abstract: We propose compact architectures of the SHA-$3$ candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the $G_i$ function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks.
BibTeX
@misc{eprint-2010-23074,
  title={Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA},
  booktitle={IACR Eprint archive},
  keywords={implementation / SHA-3, BLAKE, fully autonomous implementation, compact implementation, FPGA},
  url={http://eprint.iacr.org/2010/173},
  note={ jeanluc.beuchat@gmail.com 14749 received 1 Apr 2010, last revised 19 May 2010},
  author={Jean-Luc Beuchat and Eiji Okamoto and Teppei Yamazaki},
  year=2010
}