International Association for Cryptologic Research

International Association
for Cryptologic Research

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Senior ASIC Design and Verification Engineer
Technology Innovation Institute (TII) - Abu Dhabi, UAE

Technology Innovation Institute (TII) is a publicly funded research institute, based in Abu Dhabi, United Arab Emirates. It is home to a diverse community of leading scientists, engineers, mathematicians, and researchers from across the globe, transforming problems and roadblocks into pioneering research and technology prototypes that help move society ahead.

Cryptography Research Centre

Our work covers post-quantum cryptography, lightweight cryptography, cloud encryption schemes, secure protocols, quantum cryptographic technologies and cryptanalysis.

Position: Senior ASIC Design and Verification Engineer

  • Working on block and system-level RTL design, simulation and functional/correctness verification
  • Design, development and test of RTL IP blocks for FPGA and ASIC implementations
  • Prototyping and debugging systems on different FPGA platforms (Intel, Xilinx, Microsemi)
  • Testing of FPGA IP blocks through Chipscope/Signal analyzer tools
  • Testing of ASIC implementations through functional and formal verification
  • Defining, developing, and executing verification/coverage plans and test benches
  • Continuously improving the components (e.g., stimulus, assertions, coverage) of our design verification environment

    Skills required for the job

  • BS/MS degree in electrical/electronic/computer engineering with 5+ years of relevant experience in the industry
  • Experience using Verilog/VHDL and SystemVerilog
  • Programming and scripting skills in C/C++, Python/Tcl
  • Hands-on experience with FPGA flows, methodologies and tools
  • Experience writing test plans, portable benches, and verification IPs (transactors, monitors, speed adapters)
  • Experience with verification methods and tools including simulators, coverage collection, and waveform viewers
  • Ability to understand and integrate hardware co
  • Experience with testing of ASIC implementations through KATs, ATPG etc.
  • Knowledge of side-channel and fault-based attacks (either through actual implementations or through design)

  • Contact:
    Mehdi Messaoudi - Talent Acquisition Manager

    Last updated: 2022-06-03 posted on 2022-06-02