CHES 2005: Edinburgh, UK

Josyula R. Rao, Berk Sunar (Eds.):
Cryptographic Hardware and Embedded Systems - CHES 2005, 7th
International Workshop, Edinburgh, UK, August 29 - September 1, 2005,
Proceedings.

Side Channels I

• William Dupuy , Sébastien Kunz-Jacques :
  Resistance of Randomized Projective Coordinates Against Power Analysis . 1-14
  BibTeX
• Dakshi Agrawal , Josyula R. Rao , Pankaj Rohatgi , Kai Schramm :
  Templates as Master Keys . 15-29
  BibTeX
• Werner Schindler , Kerstin Lemke , Christof Paar :
  A Stochastic Model for Differential Side Channel Cryptanalysis . 30-46
  BibTeX

Arithmetic for Cryptanalysis

• Jean-Sébastien Coron , David Lefranc , Guillaume Poupard :
  A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis . 47-60
  BibTeX
• P. J. Green , Richard Noad , Nigel P. Smart :
  Further Hidden Markov Model Cryptanalysis . 61-74
  BibTeX

Low Resources

• Johann Großschädl , Roberto Maria Avanzi , Erkay Savas , Stefan Tillich :
  Energy-Efficient Software Implementation of Long Integer Modular Arithmetic . 75-90
  BibTeX
• Katsuyuki Okeya , Tsuyoshi Takagi , Camille Vuillaume :
  Short Memory Scalar Multiplication on Koblitz Curves . 91-105
  BibTeX
• Lejla Batina , David Hwang , Alireza Hodjat , Bart Preneel , Ingrid Verbauwhede :
  Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP . 106-118
  BibTeX

Special Purpose Hardware

• Jens Franke , Thorsten Kleinjung , Christof Paar , Jan Pelzl , Christine Priplata , Colin Stahlke :
  SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers . 119-130
  BibTeX
• Willi Geiselmann , Adi Shamir , Rainer Steinwandt , Eran Tromer :
  Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization . 131-146
  BibTeX
• Marco Bucci , Raimondo Luzzi :
  Design of Testable Random Bit Generators . 147-156
  BibTeX

Hardware Attacks and Countermeasures I

• Stefan Mangard , Norbert Pramstaller , Elisabeth Oswald :
  Successfully Attacking Masked AES Hardware Implementations . 157-171
  BibTeX
• Thomas Popp , Stefan Mangard :
  Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints . 172-186
  BibTeX
• Wieland Fischer , Berndt M. Gammel :
  Masking at Gate Level in the Presence of Glitches . 187-200
  BibTeX

Arithmetic for Cryptography

• Marcelo E. Kaihara , Naofumi Takagi :
  Bipartite Modular Multiplication . 201-210
  BibTeX
• Laszlo Hars :
  Fast Truncated Multiplication for Cryptographic Applications . 211-225
  BibTeX
• Martin Seysen :
  Using an RSA Accelerator for Modular Inversion . 226-236
  BibTeX
• Berk Sunar , David Cyganski :
  Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings. 237-249
  (electronic edition not available here) BibTeX

Side Channel II (EM)

• Catherine H. Gebotys , Simon Ho , C. C. Tiu :
  EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA. 250-264
  (electronic edition not available here) BibTeX
• Markus G. Kuhn :
  Security Limits for Compromising Emanations . 265-279
  BibTeX
• Huiyun Li , A. Theodore Markettos , Simon W. Moore :
  Security Evaluation Against Electromagnetic Analysis at Design Time . 280-292
  BibTeX

Side Channel III

• Marc Joye , Pascal Paillier , Berry Schoenmakers :
  On Second-Order Differential Power Analysis . 293-308
  BibTeX
• Eric Peeters , François-Xavier Standaert , Nicolas Donckers , Jean-Jacques Quisquater :
  Improved Higher-Order Side-Channel Attacks with FPGA Experiments . 309-323
  BibTeX

Trusted Computing

• Ulrich Kühn , Klaus Kursawe , Stefan Lucks , Ahmad-Reza Sadeghi , Christian Stüble :
  Secure Data Management in Trusted Computing . 324-338
  BibTeX

Hardware Attacks and Countermeasures II

• Sergei P. Skorobogatov :
  Data Remanence in Flash Memory Devices . 339-353
  BibTeX
• Kris Tiri , David Hwang , Alireza Hodjat , Bo-Cheng Lai , Shenglin Yang , Patrick Schaumont , Ingrid Verbauwhede :
  Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment . 354-365
  BibTeX

Hardware Attacks and Countermeasures III

• Daisuke Suzuki , Minoru Saeki , Tetsuya Ichikawa :
  DPA Leakage Models for CMOS Logic Circuits . 366-382
  BibTeX
• Sylvain Guilley , Philippe Hoogvorst , Yves Mathieu , Renaud Pacalet :
  The "Backend Duplication" Method . 383-397
  BibTeX

Efficient Hardware I

• Philipp Grabher , Dan Page :
  Hardware Acceleration of the Tate Pairing in Characteristic Three . 398-411
  BibTeX
• Tim Kerins , William P. Marnane , Emanuel M. Popovici , Paulo S. L. M. Barreto :
  Efficient Hardware for the Tate Pairing Calculation in Characteristic Three . 412-426
  BibTeX

Efficient Hardware II

• Tim Good , Mohammed Benaissa :
  AES on FPGA from the Fastest to the Smallest . 427-440
  BibTeX
• David Canright :
  A Very Compact S-Box for AES . 441-455
  BibTeX