Workshop on Cryptographic Hardware and Embedded Systems 2005 (CHES 2005)

Edinburgh, Scotland
Monday Evening August 29^th - Thursday September 1^st, 2005

[CHES 05][PROGRAM][CHES BANQUET][ACCEPTED PAPERS][ACCOMMODATIONS][TRANSPORT][EDINBURGH INFO]

Accepted Papers

Efficient hardware for the Tate pairing calculation in characteristic three
T. Kerins and W. P. Marnane and E. M. Popovici and P.S.L.M. Barreto
Data Remanence in Flash Memory Devices
Sergei Skorobogatov
Security Limits for Compromising Emanations
Markus G. Kuhn
Hardware Acceleration of the Tate Pairing in Characteristic Three
P. Grabher and D. Page
SHARK - A Realizable Special Hardware Sieving Device for Factoring 1024-bit Integers
Jens Franke and Thorsten Kleinjung and Christof Paar and Jan Pelzl and Christine Priplata and Colin Stahlke
Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
Willi Geiselmann and Adi Shamir and Rainer Steinwandt and Eran Tromer
AES on FPGA from the fastest to the smallest
T. Good and M. Benaissa
A Very Compact S-box for AES
D. Canright
Using an RSA accelerator for modular inversion
Martin Seysen
Dipolar Modular Multiplication
Marcelo E. Kaihara and Naofumi Takagi
Short-Memory Scalar Multiplication on Koblitz Curves
Katsuyuki Okeya and Tsuyoshi Takagi and Camille Vuillaume
A New Baby-Step Giant-Step Algorithm and Some Applications to hCryptanalysis
Jean-Sebastien Coron and David Lefranc and Guillaume Poupard
Fast Truncated Multiplication and its Applications in Cryptography
Laszlo Hars
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
Johann Groszschaedl and Roberto M. Avanzi and Erkay Savas and Stefan Tillich
On Second-Order Differential Power Analysis
Marc Joye and Pascal Paillier and Berry Schoenmakers
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 microprocessor
David Hwang and Lejla Batina and Alireza Hodjat and Bart Preneel and Ingrid Verbauwhede
Design of Testable Random Bit Generators
Marco Bucci and Raimondo Luzzi
Further Hidden Markov Model Cryptanalysis
P.J. Green and R. Noad and N.P. Smart
Security Evaluation Against Electromagnetic Analysis at Design Time
Huiyun Li and A. Theodore Markettos and Simon Moore
Prototype IC with WDDL and Differential Routing DPA Resistance Assessment
Kris Tiri and David Hwang and Alireza Hodjat and Bo-Cheng Lai and Shenglin Yang and Patrick Schaumont, and Ingrid Verbauwhede
DPA Leakage Models for CMOS Logic Circuits
Daisuke Suzuki and Minoru Saeki and Tetsuya Ichikawa
Secure Masking in the Presence of Glitches
Wieland Fischer and Berndt M. Gammel
Higher-Order Side-Channel Attacks: Concrete Results
Eric Peeters and Francois-Xavier Standaert and Nicolas Donckers and Jean-Jacques Quisquater
Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints
Thomas Popp and Stefan Mangard
Resistance of Randomized Projective Coordinates Against Power Analysis
William Dupuy and Sebastien Kunz-Jacques
Templates as Master Keys
Dakshi Agrawal and Josyula R Rao and Pankaj Rohatgi and Kai Schramm
Successfully Attacking Masked AES Hardware Implementations
Stefan Mangard and Norbert Pramstaller and Elisabeth Oswald
A Stochastic Model for Differential Side Channel Cryptanalysis
Werner Schindler and Kerstin Lemke and Christof Paar
EM Analysis of Rijndael and ECC on a Wireless Java-based PDA
C.Gebotys and S.Ho and C.Tiu
The "backend duplication" method.
Sylvain GUILLEY and Philippe HOOGVORST and Yves MATHIEU and Renaud PACALET
Secure Data Management in Trusted Computing
Ulrich Kuehn and Klaus Kursawe and Stefan Lucks and Ahmad-Reza Sadeghi and Christian Stueble
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
David Cyganski and Berk Sunar

Last update: May 2nd, 2005.