IACR News
Here you can see all recent updates to the IACR webpage. These updates are also available:
10 August 2023
Sunyeop Kim, Myoungsu Shin, Seonkyu Kim, Hanbeom Shin, Insung Kim, Donggeun Kwon, Dongjae Lee, Seonggyeom Kim, Deukjo Hong, Jaechul Sung, Seokhie Hong
Ghous Amjad, Kevin Yeo, Moti Yung
In certain applications, it is natural to associate signatures with specific public metadata ensuring that signatures only propagate trust with respect to only a certain set of scenarios. To solve this, we study the notion of anonymous tokens with public metadata in this work. We present a variant of RSA blind signatures with public metadata such that issuers may only generate signatures that verify for a certain choice of public metadata. We prove the security of our protocol under one-more RSA assumptions with multiple exponents that we introduce. Furthermore, we provide evidence that the concrete security bounds should be nearly identical to standard RSA blind signatures. The protocols in this paper have been proposed as a technical specification in an IRTF internet draft.
09 August 2023
The Test-of-Time award for Crypto 2008 is awarded to:
A Framework for Efficient and Composable Oblivious Transfer, by Chris Peikert, Vinod Vaikuntanathan and Brent Waters, for the creation of a simple framework for achieving efficient UC composable protocols that can be realized under a variety of concrete assumptions, introducing a powerful notion of dual-mode encryption and allowing for the first time to create bandwidth efficient Regev encryption.
For more information, see https://www.iacr.org/testoftime.
Congratulations to the winners!
08 August 2023
Roorkee, India, 14 December - 17 December 2023
Submission deadline: 1 September 2023
Notification: 15 October 2023
Sydney, Australia, 15 April - 17 April 2024
Submission deadline: 1 October 2023
Notification: 15 December 2023
07 August 2023
Sonia Belaïd, Gaëtan Cassiers, Camille Mutschler, Matthieu Rivain, Thomas Roche, François-Xavier Standaert, Abdul Rahman Taleb
In this paper, we present a complete methodology describing the steps to turn an abstract masking scheme proven secure in a theoretical leakage model into a physical implementation satisfying provable security against side-channel attacks in practice. We propose new tools to enforce or relax the physical assumptions the indeal noisy leakage model rely on and provide novel ways of including them in a physical implementation. We also highlight the design goals for an embedded device to reach high levels of proven security, discussing the limitations and open problems of the practical usability of the leakage models. Our goal is to show that it is possible to bridge theory and practice and to motivate further research to fully close the gap and get practical implementations proven secure against side-channel attacks on a physical device without any ideal assumption about the leakage.
Thomas Decru, Luciano Maino, Antonio Sanso
Sourav Das, Zhuolun Xiang, Alin Tomescu, Alexander Spiegelman, Benny Pinkas, Ling Ren
Colin O'Flynn
The paper also introduces an iCE40 based Time-to-Digital Converter (TDC), which is used to visualize the glitch inserted by the EMFI tool. This demonstrates the internal voltage perturbations between voltage, body biasing injection (BBI), and EMFI all result in similar waveforms. In addition, a link between an easy-to-measure external voltage measurement and the internal measurement is made. Attacks are also made on a hardware AES engine, and a soft-core RISC-V processor, all running on the same iCE40 FPGA.
The platform is used to demonstrate several aspects of fault injection, including that the spatial positioning of the EMFI probe can impact the glitch strength, and that the same physical device may require widely different glitch parameters when running different designs.
Xinyi Ji, Jiankuo Dong, Pinchang Zhang, Deng Tonggui, Hua Jiafeng, Fu Xiao
Inam ul Haq, Jian Wang, Youwen Zhu, Sheharyar Nasir
Abhiram Kothapalli, Srinath Setty
CycleFold’s starting point is the observation that folding-scheme-based recursive arguments can be efficiently instantiated without a cycle of elliptic curves—except for a few scalar multiplications in their verifiers (2 in Nova, 1 in HyperNova, and 3 in ProtoStar). Accordingly, CycleFold uses the second curve in the cycle to merely represent a single scalar multiplication ($\approx$1,000--1,500 multiplication gates). CycleFold then folds invocations of that tiny circuit on the first curve in the cycle. This is nearly an order of magnitude improvement over the prior state-of-the-art in terms of circuit sizes on the second curve. CycleFold is particularly beneficial when instantiating folding-scheme-based recursive arguments over “half pairing” cycles (e.g., BN254/Grumpkin) as it keeps the circuit on the non-pairing-friendly curve minimal. The running instance in a CycleFold-based recursive argument consists of an instance on the first curve and a tiny instance on the second curve. Both instances can be proven using a zkSNARK defined over the scalar field of the first curve.
On the conceptual front, with CycleFold, an IVC construction and nor its security proof has to explicitly reason about the cycle of elliptic curves. Finally, due to its simplicity, CycleFold-based recursive argument can be more easily be adapted to support parallel proving with the so-called "binary tree" IVC.
Shweta Agrawal, Junichi Tomida, Anshu Yadav
$$\sum_{i \in [n]}\sum_{j \in [N_{i}]}h_{i}(\vec{x}_{i,j})^{\top}\vec{z}_{i,j} \text{ iff } g_{i}(\vec{y}_{i}) =0 \text{ for all } i \in [n]$$ Previously, the only known attribute based MIFE was for the inner product functionality (Abdalla et al.~Asiacrypt 2020), where additionally, $\vec{y}_i$ had to be fixed during setup and must remain the same for all ciphertexts in a given slot. Our attribute based MIFE implies the notion of multi-input {\it attribute based encryption} (\miabe) recently studied by Agrawal, Yadav and Yamada (Crypto 2022) and Francati, Friolo, Malavolta and Venturi (Eurocrypt 2023), for a conjunction of predicates represented as arithmetic branching programs (ABP). Along the way, we also provide the first constructions of multi-client FE (MCFE) and dynamic decentralized FE (DDFE) for the AWS functionality. Previously, the best known MCFE and DDFE schemes were for inner products (Chotard et al.~ePrint 2018, Abdalla, Benhamouda and Gay, Asiacrypt 2019, and Chotard et al.~Crypto 2020). Our constructions are based on pairings and proven selectively secure under the matrix DDH assumption.
06 August 2023
University of New Brunswick, Fredericton, Canada
Closing date for applications:
Contact: Kalikinkar Mandal (kmandal@unb.ca)
University at Albany, SUNY; New York, USA
Closing date for applications:
Contact: Please contact Dr. Seetal Potluri (spotluri@albany.edu) for more information.
University at Albany, SUNY; New York, USA
Closing date for applications:
Contact: Please contact Dr. Seetal Potluri (spotluri@albany.edu) for more information.
University of Birmingham, UK
This is an exciting opportunity to join the University of Birmingham’s Centre for Cyber Security and Privacy on the EPSRC funded project ‘IOTEE: Securing and analysing trusted execution beyond the CPU, led by Prof David Oswald and Prof Mark Ryan.
Trusted Execution Environments (TEEs) allow users to run their software in a secure enclave while assuring the integrity and confidentiality of data and applications. However, cloud computing these days relies heavily on peripherals such as GPUs, NICs, and FPGAs. Extending the security guarantees of CPU-based TEEs to such accelerators is currently not possible. New technologies are being proposed to address this, notably the PCIe Trusted Device Interface Security Protocol (TDISP). In this project, together with researchers at the University of Southampton, we will thoroughly evaluate the security guarantees of this new PCIe standard and its ability to provide trusted execution against strong adversaries. This will involve the use of formal modelling, as well as researching various software and hardware attacks and countermeasures against them.
This project is aligned with the UK's Research Institute for Secure Hardware and Embedded System (RISE), and the successful candidate will have the chance to disseminate their findings at relevant events. They will also have the opportunity to closely work with the team of Dr Ahmad Atamli and Prof Vladi Sassone (both University of Southampton) as the main academic project partner.
Candidates should have a PhD e.g. in cyber security, computer science, or electrical engineering. They should have experience in embedded security, binary analysis, physical attacks such as side-channel analysis and fault injection, and/or formal modelling; evidenced through publications in highly ranked conferences/journals in the field. In exceptional circumstances, we will also consider candidates without a PhD but with equivalent industry experience.
Applications are accepted until14 August 2023, using the following link https://edzz.fa.em3.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_6001/job/2681/
Closing date for applications:
Contact: Informal enquiries can be made to David Oswald: d.f.oswald@bham.ac.uk
More information: https://edzz.fa.em3.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_6001/job/2681/
Technology Innovation Institute (TII)
Technology Innovation Institute (TII) is a publicly funded research institute, based in Abu Dhabi, United Arab Emirates. It is home to a diverse community of leading scientists, engineers, mathematicians, and researchers from across the globe, transforming problems and roadblocks into pioneering research and technology prototypes that help move society ahead.
Cryptography Research Center
In our connected digital world, secure and reliable cryptography is the foundation of digital information security and data integrity. We address the world’s most pressing cryptographic questions. Our work covers post-quantum cryptography, lightweight cryptography, cloud encryption schemes, secure protocols, quantum cryptographic technologies and cryptanalysis.
Job Description:
We are seeking a skilled and motivated individual to join our team in a hardware engineer internship position with expertise in hardware acceleration. The ideal candidate will have experience working with fully-homomorphic encryption and a strong background on FPGA design for acceleration.
Closing date for applications:
Contact:
Dr. Kashif Nawaz - Director
Kashif.nawaz@tii.ae
04 August 2023
Aikata Aikata, Ahmet Can Mert, Sunmin Kwon, Maxim Deryabin, Sujoy Sinha Roy
Experimental results demonstrate that REED 2.5D integrated circuit consumes 177 mm$^2$ chip area, 82.5 W average power in 7nm technology, and achieves an impressive speedup of up to 5,982$\times$ compared to a CPU (24-core 2$\times$Intel X5690), and 2$\times$ better energy efficiency and 50\% lower development cost than state-of-the-art ASIC accelerator. To evaluate its practical impact, we are the $first$ to benchmark an encrypted deep neural network training. Overall, this work successfully enhances the practicality and deployability of fully homomorphic encryption in real-world scenarios.