IACR News
Here you can see all recent updates to the IACR webpage. These updates are also available:
21 December 2020
Claude Carlet
Alex Ozdemir, Fraser Brown, Riad S. Wahby
To make our approach concrete we create CirC, an infrastructure for building compilers to EQCs. CirC makes it easy to add support for new EQCs: we build support for two, one used by the PL community and one used by the cryptography community, in $\approx$2000 LOC. Its also easy to extend CirC to support new source languages: we build a feature complete compiler for a cryptographic language in one week and $\approx$700 LOC, whereas the reference compiler for the same language took years to write, comprises $\approx$24000 LOC, and produces worse-performing output than our compiler. Finally, CirC enables novel applications that combine multiple EQCs. For example, we build the first pipeline that (1) automatically identifies bugs in programs, then (2) automatically constructs cryptographic proofs of the bugs existence.
Timothy J. Hodges, Hari R. Iyer
Panos Kampanakis, Peter Panburana, Michael Curcio, Chirag Shroff
Iraklis Symeonidis, Dragos Rotaru, Mustafa A. Mustafa, Bart Mennink, Panos Papadimitratos
Hangi Kim, Yongjin Jeon, Giyoon Kim, Jongsung Kim, Bo-Yeon Sim, Dong-Guk Han, Hwajeong Seo, Seonggyeom Kim, Seokhie Hong, Jaechul Sung, Deukjo Hong
Jung Hee Cheon, Seungwan Hong, and Duhyeong Kim
Conor McMenamin, Vanesa Daza, Matteo Pontecorvi
Hankyung Ko, Ingeun Lee, Seunghwa Lee, Jihye Kim, Hyunok Oh
Tung Chou
Alessandro Baccarini, Marina Blanton, Chen Yuan
Changhui Hu, Jin Li, Zheli Liu, Xiaojie Guo, Yu Wei, Xuan Guang, Grigorios Loukides, Changyu Dong
Loïc Ferreira
20 December 2020
Daejeon, South Korea, 20 May - 22 May 2021
Submission deadline: 3 March 2021
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Submission deadline: 8 March 2021
Tokyo Institute of Technology, School of Computing, Tokyo, Japan
Closing date for applications:
Contact: Keisuke Tanaka, Professor, Chair of Department of Mathematical and Computing Science, School of Computing (Email: keisuke@is.titech.ac.jp)
More information: https://jrecin.jst.go.jp/seek/SeekJorDetail?id=D120120992&ln_jor=1
Tokyo Institute of Technology, School of Computing, Tokyo, Japan
Closing date for applications:
Contact: Keisuke Tanaka, Professor, Chair of Department of Mathematical and Computing Science, School of Computing (Email: keisuke@is.titech.ac.jp)
More information: https://jrecin.jst.go.jp/seek/SeekJorDetail?id=D120120988&ln_jor=1
POLE LEONARD DE VINCI, Paris La Défense
Closing date for applications:
Contact: APPLICATION PROCEDURE: Please provide your CV and a cover letter describing your research activities. Qualified candidates need to send their application package by email to recrutement@devinci.fr. Contacts: - Cyril Grunspan (cyril.grunspan@devinci.fr) - Jean Rohmer (jean.rohmer@devinci.fr)
More information: https://www.devinci.fr/
CentraleSupélec, IETR Lab; Rennes, France
The IETR Lab in Rennes (FR) is looking for a motivated master student on the last year of their degree for a 5-6 month internship, which can serve as the mandatory internship to finish your degree.
CentraleSupélec is a top Engineering school in France with a established tradition of excellence in Cybersecurity. It is a great place for an internship at the IETR CNRS-affiliated laboratory in Rennes, a world-class research and innovation pole in cybersecurity.
Topic
To protect critical infrastructures and sensitive data managed by CPS running Machine Learning algorithms, we need robust implementations able to resist attacks. To this end, we are studying the vulnerabilities that physical SCA attacks pose to DNN/CNN accelerators in FPGAs. In this internship you will: (1) review the literature on power attacks to ML implementations and (2) build an experimental set-up to reverse engineer DNN accelerators using (power/EM) side-channel leakage from heterogeneous devices like Zynq SoC/MPSoC.
Profile
Master student in Computer/Electrical Eng, Electronics or Computer Science with strong background in one or various of the following topics
- HW security, SCA attacks
- HDL/HLS design for FPGAs (pref. Vivado), experience with actual implementations, use of lab. instruments as oscilloscopes
- DNN/CNN implementation in FPGAs
- Familiarity with C/C++/Python programming, Linux/Git as dev. environment
French is not required.
There might be options to continue working towards a PhD after the internship.
Information
- Location: CentraleSupélec, IETR Lab, Rennes (FR)
- Starting date: flexible, anytime from Feb/March
- Duration: 5-6 months
- Stipend: according to regulations, 550-600€/month
Deadline: mid January (interviews running now)
To apply: https://www.ietr.fr/spip.php?article2150
Contact for more info. regarding COVID-19 situation.
Closing date for applications:
Contact: Rubén Salvador: ruben.salvador@centralesupelec.org
More information: https://www.ietr.fr/spip.php?article2150
University of Notre Dame, Notre Dame, IN, USA
Closing date for applications:
Contact: Taeho Jung
More information: https://sites.nd.edu/taeho-jung/