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Paper: Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks

Authors:
Xiaolin Xu
Bicky Shakya
Mark M. Tehranipoor
Domenic Forte
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DOI: 10.1007/978-3-319-66787-4_10
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Conference: CHES 2017
Abstract: Logic locking has emerged as a promising technique for protecting gate-level semiconductor intellectual property. However, recent work has shown that such gate-level locking techniques are vulnerable to Boolean satisfiability (SAT) attacks. In order to thwart such attacks, several SAT-resistant logic locking techniques have been proposed, which minimize the discriminating ability of input patterns to rule out incorrect keys. In this work, we show that such SAT-resistant logic locking techniques have their own set of unique vulnerabilities. In particular, we propose a novel “bypass attack” that ensures the locked circuit works even when an incorrect key is applied. Such a technique makes it possible for an adversary to be oblivious to the type of SAT-resistant protection applied on the circuit, and still be able to restore the circuit to its correct functionality. We show that such a bypass attack is feasible on a wide range of benchmarks and SAT-resistant techniques, while incurring minimal run-time and area/delay overhead. Binary decision diagrams (BDDs) are utilized to analyze the proposed bypass attack and assess tradeoffs in security vs overhead of various countermeasures.
BibTeX
@inproceedings{ches-2017-28917,
  title={Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks},
  booktitle={Cryptographic Hardware and Embedded Systems – CHES 2017},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={10529},
  pages={189-210},
  doi={10.1007/978-3-319-66787-4_10},
  author={Xiaolin Xu and Bicky Shakya and Mark M. Tehranipoor and Domenic Forte},
  year=2017
}