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Paper: BipBip: A Low-Latency Tweakable Block Cipher with Small Dimensions

Authors:
Yanis Belkheyar , Digital Security Group, Radboud University, Nijmegen, The Netherlands
Joan Daemen , Digital Security Group, Radboud University, Nijmegen, The Netherlands
Christoph Dobraunig , Intel Labs, Hillsboro, USA
Santosh Ghosh , Intel Labs, Hillsboro, USA
Shahram Rasoolzadeh , Digital Security Group, Radboud University, Nijmegen, The Netherlands
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DOI: 10.46586/tches.v2023.i1.326-368
URL: https://tches.iacr.org/index.php/TCHES/article/view/9955
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Abstract: Recently, a memory safety concept called Cryptographic Capability Computing (C3) has been proposed. C3 is the first memory safety mechanism that works without requiring extra storage for metadata and hence, has the potential to significantly enhance the security of modern IT-systems at a rather low cost. To achieve this, C3 heavily relies on ultra-low-latency cryptographic primitives. However, the most crucial primitive required by C3 demands uncommon dimensions. To partially encrypt 64-bit pointers, a 24-bit tweakable block cipher with a 40-bit tweak is needed. The research on low-latency tweakable block ciphers with such small dimensions is not very mature. Therefore, designing such a cipher provides a great research challenge, which we take on with this paper. As a result, we present BipBip, a 24-bit tweakable block cipher with a 40-bit tweak that allows for ASIC implementations with a latency of 3 cycles at a 4.5 GHz clock frequency on a modern 10 nm CMOS technology.
BibTeX
@article{tches-2022-32689,
  title={BipBip: A Low-Latency Tweakable Block Cipher with Small Dimensions},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universit├Ąt Bochum},
  volume={2023, Issue 1},
  pages={326-368},
  url={https://tches.iacr.org/index.php/TCHES/article/view/9955},
  doi={10.46586/tches.v2023.i1.326-368},
  author={Yanis Belkheyar and Joan Daemen and Christoph Dobraunig and Santosh Ghosh and Shahram Rasoolzadeh},
  year=2022
}