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A Low-Latency High-Order Arithmetic to Boolean Masking Conversion

Authors:
Jiangxue Liu , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Cankun Zhao , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Shuohang Peng , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Bohan Yang , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Hang Zhao , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Xiangdong Han
Min Zhu , Wuxi Micro Innovation Integrated Circuit Design Co., Ltd., Wuxi, China
Shaojun Wei , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
Leibo Liu , Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University, Beijing, China
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DOI: 10.46586/tches.v2024.i2.630-653
URL: https://tches.iacr.org/index.php/TCHES/article/view/11441
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Abstract: Masking, an effective countermeasure against side-channel attacks, is commonly applied in modern cryptographic implementations. Considering cryptographic algorithms that utilize both Boolean and arithmetic masking, the conversion algorithm between arithmetic masking and Boolean masking is required. Conventional high-order arithmetic masking to Boolean masking conversion algorithms based on Boolean circuits suffer from performance overhead, especially in terms of hardware implementation. In this work, we analyze high latency for the conversion and propose an improved high-order A2B conversion algorithm. For the conversion of 16-bit variables, the hardware latency can be reduced by 47% in the best scenario. For the case study of second-order 32-bit conversion, the implementation results show that the improved scheme reduces the clock cycle latency by 42% in hardware and achieves a 30% speed performance improvement in software. Theoretically, a security proof of arbitrary order is provided for the proposed high-order A2B conversion. Experimental validations are performed to verify the second-order DPA resistance of second-order implementation. The Test Vector Leakage Assessment does not observe side-channel leakage for hardware and software implementations.
BibTeX
@article{tches-2024-34064,
  title={A Low-Latency High-Order Arithmetic to Boolean Masking Conversion},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universit├Ąt Bochum},
  volume={024 No. 2},
  pages={630-653},
  url={https://tches.iacr.org/index.php/TCHES/article/view/11441},
  doi={10.46586/tches.v2024.i2.630-653},
  author={Jiangxue Liu and Cankun Zhao and Shuohang Peng and Bohan Yang and Hang Zhao and Xiangdong Han and Min Zhu and Shaojun Wei and Leibo Liu},
  year=2024
}