International Association for Cryptologic Research

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Fast Transciphering Via Batched And Reconfigurable LUT Evaluation

Authors:
Leonard Schild
Aysajan Abidin
Bart Preneel
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DOI: 10.46586/tches.v2024.i4.205-230
URL: https://tches.iacr.org/index.php/TCHES/article/view/11789
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Abstract: Fully homomorphic encryption provides a way to perform computations in a privacy preserving manner. However, despite years of optimization, modern methods may still be too computationally expensive for devices limited by speed or memory constraints. A paradigm that may bridge this gap consists of transciphering: as fully homomorphic schemes can perform most computations obliviously, they can also execute the decryption circuit of any conventional block or stream cipher. Hence, less powerful systems may continue to encrypt their data using classical ciphers that may offer hardware support (e.g., AES) and outsourcing the task of transforming the ciphertexts into their homomorphic equivalent to more powerful systems. In this work, we advance transciphering methods that leverage accumulator-based schemes such as Torus-FHE (TFHE) or FHEW. To this end, we propose a novel method to homomorphically evaluate look-up tables in a setting in which encrypted digits are provided on base 2. At a high level, our method relies on the fact that functions with binary range, i.e., mapping values to {0, 1}, can be evaluated at the same computational cost as negacyclic functions, relying only on the default functionality of accumulator based schemes. To test our algorithm, we implement the AES-128 encryption circuit in OPENFHE and report timings of 67 s for a single block, which is 25% faster than the state of the art and in general, up to 300% faster than other recent works. Furthermore, we achieve this speedup without relying on an instantiation that leverages a power of 2 modulus and can exploit the natural modulo arithmetic of modern processors.
BibTeX
@article{tches-2024-34463,
  title={Fast Transciphering Via Batched And Reconfigurable LUT Evaluation},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universität Bochum},
  volume={2024},
  pages={205-230},
  url={https://tches.iacr.org/index.php/TCHES/article/view/11789},
  doi={10.46586/tches.v2024.i4.205-230},
  author={Leonard Schild and Aysajan Abidin and Bart Preneel},
  year=2024
}