International Association
for Cryptologic Research

Zihao Wei , School of Cryptology, Data Communication Science and Technology Research Institute

Siwei Sun , School of Cryptology, State Key Laboratory of Cryptology

Fengmei Liu , Data Communication Science and Technology Research Institute

Lei Hu , Key Laboratory of Cyberspace Security Defense, School of Cyber Security

Zhiyu Zhang , School of Cryptology

DOI: 10.62056/akmpdkp10

URL: https://cic.iacr.org/p/1/4/20

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Boolean formula minimization is a notoriously hard problem. Circuit minimization, typically studied in the context of a much broader subject known as synthesis and optimization of circuits, introduces another layer of complexity since ultimately those technology-independent representations (e.g., Boolean formulas and truth tables) has to be transformed into a netlist of cells of the target technology library. To manage those complexities, the industrial community typically separates the synthesis process into two steps: technology-independent optimization and technology mapping. In each step, this approach only tries to find the local optimal solution and relies heavily on heuristics rather than a systematic search. However, for small S-boxes, a more systematic exploration of the design space is possible. Aiming at the global optimum, we propose a method which can synthesize a truth table for a small S-box directly into a netlist of the cells of a given technology library. Compared with existing technology-dependent synthesis tools like LIGHTER and PEIGEN, our method produces improved results for many S-boxes with respect to circuit area. In particular, by applying our method to the GF(2^4)-inverter involved in the tower field implementation of the AES S-box, we obtain the currently known lightest implementation of the AES S-box. The search framework can be tweaked to take circuit delay into account. As a result, we find implementations for certain S-boxes with both latency and area improved.