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Higher-Order Time Sharing Masking

Authors:
Dilip Kumar S. V.
Siemen Dhooghe
Josep Balasch
Benedikt Gierlichs
Ingrid Verbauwhede
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DOI: 10.46586/tches.v2025.i2.235-267
URL: https://tches.iacr.org/index.php/TCHES/article/view/12047
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Abstract: At CHES 2024, Time Sharing Masking (TSM) was introduced as a novel low-latency masking technique for hardware circuits. TSM offers area and randomness efficiency, as well as glitch-extended PINI security, but it is limited to first-order security. We address this limitation and generalize TSM to higher-order security while maintaining all of TSM’s advantages. Additionally, we propose an area-latency tradeoff. We prove HO-TSM glitch-extended PINI security and successfully evaluate our circuits using formal verification tools. Furthermore, we demonstrate area- and latency-efficient implementations of the AES S-box, which do not exhibit leakage in TVLA on FPGA. Our proposed tradeoff enables a first-order secure implementation of a complete AES-128 encryption core with 92 kGE, 920 random bits per round, and 20 cycles of latency, which does not exhibit leakage in TVLA on FPGA.
BibTeX
@article{tches-2025-35227,
  title={Higher-Order Time Sharing Masking},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universität Bochum},
  volume={2025},
  pages={235-267},
  url={https://tches.iacr.org/index.php/TCHES/article/view/12047},
  doi={10.46586/tches.v2025.i2.235-267},
  author={Dilip Kumar S. V. and Siemen Dhooghe and Josep Balasch and Benedikt Gierlichs and Ingrid Verbauwhede},
  year=2025
}