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Fixslicing AES-like Ciphers: New bitsliced AES speed records on ARM-Cortex M and RISC-V
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| Abstract: | The fixslicing implementation strategy was originally introduced as a new representation for the hardware-oriented GIFT block cipher to achieve very efficient software constant-time implementations. In this article, we show that the fundamental idea underlying the fixslicing technique is not of interest only for GIFT, but can be applied to other ciphers as well. Especially, we study the benefits of fixslicing in the case of AES and show that it allows to reduce by 52% the amount of operations required by the linear layer when compared to the current fastest bitsliced implementation on 32-bit platforms. Overall, we report that fixsliced AES-128 allows to reach 80 and 91 cycles per byte on ARM Cortex-M and E31 RISC-V processors respectively (assuming pre-computed round keys), improving the previous records on those platforms by 21% and 26%. In order to highlight that our work also directly improves masked implementations that rely on bitslicing, we report implementation results when integrating first-order masking that outperform by 12% the fastest results reported in the literature on ARM Cortex-M4. Finally, we demonstrate the genericity of the fixslicing technique for AES-like designs by applying it to the Skinny-128 tweakable block ciphers. |
Video from TCHES 2020
BibTeX
@article{tches-2020-30772,
title={Fixslicing AES-like Ciphers: New bitsliced AES speed records on ARM-Cortex M and RISC-V},
journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
publisher={Ruhr-Universität Bochum},
volume={2021, Issue 1},
pages={402-425},
url={https://tches.iacr.org/index.php/TCHES/article/view/8739},
doi={10.46586/tches.v2021.i1.402-425},
author={Alexandre Adomnicai and Thomas Peyrin},
year=2020
}