International Association for Cryptologic Research

International Association
for Cryptologic Research


Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure

Shoei Nashimoto , Mitsubishi Electric Corporation, Japan; Tohoku University, Japan
Daisuke Suzuki , Mitsubishi Electric Corporation, Japan
Rei Ueno , Tohoku University, Japan
Naofumi Homma , Tohoku University, Japan
DOI: 10.46586/tches.v2022.i1.28-68
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Abstract: RISC-V is equipped with physical memory protection (PMP) to prevent malicious software from accessing protected memory regions. PMP provides a trusted execution environment (TEE) that isolates secure and insecure applications. In this study, we propose a side-channel-assisted fault-injection attack to bypass isolation based on PMP. The proposed attack scheme involves extracting successful glitch parameters for fault injection from side-channel information under crossdevice conditions. A proof-of-concept TEE compatible with PMP in RISC-V was implemented, and the feasibility and effectiveness of the proposed attack scheme was validated through experiments in TEEs. The results indicate that an attacker can bypass the isolation of the TEE and read data from the protected memory region In addition, we experimentally demonstrate that the proposed attack applies to a real-world TEE, Keystone. Furthermore, we propose a software-based countermeasure that prevents the proposed attack.
  title={Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universit├Ąt Bochum},
  volume={2022, Issue 1},
  author={Shoei Nashimoto and Daisuke Suzuki and Rei Ueno and Naofumi Homma},