## CryptoDB

### Paper: Transitional Leakage in Theory and Practice: Unveiling Security Flaws in Masked Circuits

Authors: Nicolai Müller , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany David Knichel , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany Pascal Sasdrich , Ruhr University Bochum, Horst Görtz Institute for IT Security, Bochum, Germany Amir Moradi , University of Cologne, Institute for Computer Science, Cologne, Germany DOI: 10.46586/tches.v2022.i2.266-288 URL: https://tches.iacr.org/index.php/TCHES/article/view/9488 Search ePrint Search Google Accelerated by the increased interconnection of highly accessible devices, the demand for effective and efficient protection of hardware designs against Side-Channel Analysis (SCA) is ever rising, causing its topical relevance to remain immense in both, academia and industry. Among a wide range of proposed countermeasures against SCA, masking is a highly promising candidate due to its sound foundations and well-understood security requirements. In addition, formal adversary models have been introduced, aiming to accurately capture real-world attack scenarios while remaining sufficiently simple to efficiently reason about the SCA resilience of designs. Here, the d-probing model is the most prominent and well-studied adversary model. Its extension, introduced as the robust d-probing model, covers physical defaults occurring in hardware implementations, particularly focusing on combinational recombinations (glitches), memory recombinations (transitions), and routing recombinations (coupling).With increasing complexity of modern cryptographic designs and logic circuits, formal security verification becomes ever more cumbersome. This started to spark innovative research on automated verification frameworks. Unfortunately, these verification frameworks mostly focus on security verification of hardware circuits in the presence of glitches, but remain limited in identification and verification of transitional leakage. To this end, we extend SILVER, a recently proposed tool for formal security verification of masked logic circuits, to also detect and verify information leakage resulting from combinations of glitches and transitions. Based on extensive case studies, we further confirm the accuracy and practical relevance of our methodology when assessing and verifying information leakage in hardware implementations.
##### BibTeX
@article{tches-2022-32005,
title={Transitional Leakage in Theory and Practice: Unveiling Security Flaws in Masked Circuits},
journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
publisher={Ruhr-Universität Bochum},
volume={2022, Issue 2},
pages={266-288},
url={https://tches.iacr.org/index.php/TCHES/article/view/9488},
doi={10.46586/tches.v2022.i2.266-288},
author={Nicolai Müller and David Knichel and Pascal Sasdrich and Amir Moradi},
year=2022
}