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Papers from CHES 2007
Year
Venue
Title
2007
CHES
A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter
Joshua Jaffe
2007
CHES
A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations
Andrey Bogdanov
Thomas Eisenbarth
Andy Rupp
2007
CHES
AES Encryption Implementation and Analysis on Commodity Graphics Processing Units
Owen Harrison
John Waldron
2007
CHES
Arithmetic Operators for Pairing-Based Cryptography
★
Best Paper
Jean-Luc Beuchat
Nicolas Brisebarre
Jérémie Detrey
Eiji Okamoto
2007
CHES
CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method
Tetsuya Izu
Jun Kogure
Takeshi Shimoyama
2007
CHES
Collision Attacks on AES-Based MAC: Alpha-MAC
Alex Biryukov
Andrey Bogdanov
Dmitry Khovratovich
Timo Kasper
2007
CHES
Collision Search for Elliptic Curve Discrete Logarithm over GF(2<sup> <i>m</i> </sup>) with FPGA
Guerric Meurice de Dormale
Philippe Bulens
Jean-Jacques Quisquater
2007
CHES
Contactless authentication protocols for MRTDs
★
Invited talk
Kim Nguyen
2007
CHES
Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings
2007
CHES
Differential Behavioral Analysis
Bruno Robisson
Pascal Manet
2007
CHES
DPA-Resistance Without Routing Constraints?
Benedikt Gierlichs
2007
CHES
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
Thomas Popp
Mario Kirschbaum
Thomas Zefferer
Stefan Mangard
2007
CHES
FPGA Design of Self-certified Signature Verification on Koblitz Curves
Kimmo U. Järvinen
Juha Forsten
Jorma Skyttä
2007
CHES
FPGA Intrinsic PUFs and Their Use for IP Protection
Jorge Guajardo
Sandeep S. Kumar
Geert Jan Schrijen
Pim Tuyls
2007
CHES
Gaussian Mixture Models for Higher-Order Side Channel Analysis
Kerstin Lemke-Rust
Christof Paar
2007
CHES
High-Speed True Random Number Generation with Logic Gates Only
Markus Dichtl
Jovan Dj. Golic
2007
CHES
Highly Regular Right-to-Left Algorithms for Scalar Multiplication
Marc Joye
2007
CHES
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
Daisuke Suzuki
2007
CHES
Information Theoretic Evaluation of Side-Channel Resistant Logic Styles
François Macé
François-Xavier Standaert
Jean-Jacques Quisquater
2007
CHES
MAME: A Compression Function with Reduced Hardware Requirements
Hirotaka Yoshida
Dai Watanabe
Katsuyuki Okeya
Jun Kitahara
Hongjun Wu
Özgül Küçük
Bart Preneel
2007
CHES
Masking and Dual-Rail Logic Don't Add Up
Patrick Schaumont
Kris Tiri
2007
CHES
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Stefan Lemsitzer
Johannes Wolkerstorfer
Norbert Felber
Matthias Braendli
2007
CHES
On the Implementation of a Fast Prime Generation Algorithm
Christophe Clavier
Jean-Sébastien Coron
2007
CHES
On the Power of Bitslice Implementation on Intel Core2 Processor
Mitsuru Matsui
Junko Nakajima
2007
CHES
Power Analysis Resistant AES Implementation with Instruction Set Extensions
Stefan Tillich
Johann Großschädl
2007
CHES
Power and EM Attacks on Passive 13.56 MHz RFID Devices
Michael Hutter
Stefan Mangard
Martin Feldhofer
2007
CHES
PRESENT: An Ultra-Lightweight Block Cipher
Andrey Bogdanov
Lars R. Knudsen
Gregor Leander
Christof Paar
Axel Poschmann
Matthew J. B. Robshaw
Yannick Seurin
C. Vikkelsoe
2007
CHES
RF-DNA: Radio-Frequency Certificates of Authenticity
Gerald DeJean
Darko Kirovski
2007
CHES
RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
O. Savry
F. Pebay-Peyroula
F. Dehmas
G. Robert
J. Reverdy
2007
CHES
Secret External Encodings Do Not Prevent Transient Fault Analysis
Christophe Clavier
2007
CHES
Side Channel Cryptanalysis of a Higher Order Masking Scheme
★
Best Paper
Jean-Sébastien Coron
Emmanuel Prouff
Matthieu Rivain
2007
CHES
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
Reouven Elbaz
David Champagne
Ruby B. Lee
Lionel Torres
Gilles Sassatelli
Pierre Guillemin
2007
CHES
Trustworthy Hardware
★
Invited talk
Pankaj Rohatgi
2007
CHES
Two New Techniques of Side-Channel Cryptanalysis
Alex Biryukov
Dmitry Khovratovich